1. Field of the Invention
The present invention relates to method of testing a semiconductor device, and more particularly, to a method of driving and testing word lines of a dynamic random access memory.
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories have millions of memory cells. As shown in FIG. 1, every memory cell MC has a transistor T and a capacitor C, a gate terminal of the selected transistor T is controlled by a word line WL. When the word line WL is selected, the corresponding transistor T will be turned on. Then, The electric charge storied in the capacitor is sent to the bit line BL and sense amplifier SA, after compares on by the sense amplifier SA, the amplifier SA outputs a logic 0 or logic 1 signal. The logic 0 or logic 1 signal represents the data stored in the memory cell MC. Finally, the output signal is read by the I/O data line.
FIG. 2 shows a driving circuit of a DRAM, showing how to turn on a predetermined word line. A driving circuit of a word line is composed of two PMOS transistors P1 and P2. the PMOS P2 is a backup transistor. When a word line WL0 is selected, a control signal of a control line Dout will be pulled down to a low potential level by a testing unit 11, and a driving signal of a driving line WLDV will be raised to a high potential level Vpp. When the PMOS transistors P1 and P2 are switched on, the driving signal Vpp is sent to the word line WL0 through PMOS transistor P1. When a precharge commend is proceeded by the testing unit 11, the control signal of the control line DOUT will be raised to a high potential level, the driving signal of the driving line WLDV will be pulled down from high potential level to low potential level (VGND), and the word line will WL0 be turned off.
FIG. 3 shows a schemetic layout diagram, which shows a plurality of driving circuits corresponding to a block of word lines in a DRAM, according to FIG. 3, there are 16 word lines WL0˜WLF in the picture. Every word line in the memory is driven by a corresponding driving circuit, and the driving circuits 10 are controlled by control lines DOUT0˜DOUT3 and driving lines WLDV0˜WLDV3 to turn on or turn off the word lines WL0˜WLF. For example, the control line DOUT0 is coupled to the driving circuits 10 of the first to the fourth word lines WL0˜WL3 of the block word lines WL0˜WLF. The connection of the remaining word lines are the same and the description is omitted here. When the control line DOUT0 and the driving line WLDV0 is turned on, the word line WL0 is turned on.
In the conventional method, only one control line and one driving line can be turned on in a block of DRAM. First, a control line DOUT0 and a driving line WLDV0 is enabled, meaning the control signal of the control line DOUT0 is pulled down to a low potential level and the driving line is pulled to a high voltage level. After a delay time, a precharge commend is proceeded to close and disable the word line WL0, the control line WL0 and the driving line WLDV0, the control signal of the control line DOUT0 is pulled high and the driving signal of the driving line pulled low. Next, a following word line is turned on in the same way. Hence only one word line in a block word lines is turned on at one time. This method is time consuming when turning on all the word lines in a DRAM, causing throughput to suffer.